1. Field of the Invention
The invention relates generally to semiconductor structures. More particularly, the invention relates to semiconductor structures with enhanced manufacturability.
2. Description of the Related Art
Semiconductor structures typically include semiconductor devices that are located and formed within and upon a semiconductor substrate. A particularly common semiconductor structure is a complementary metal oxide semiconductor (CMOS) structure. A CMOS structure comprises a complementary doped pair of field effect devices, such as field effect transistor devices, located and formed within a single semiconductor substrate. The single semiconductor substrate may comprise a single crystallographic orientation region or multiple crystallographic orientation regions.
CMOS structures are desirable within the semiconductor fabrication art insofar as CMOS devices typically consume less power than semiconductor devices that comprise other than CMOS devices. In addition, CMOS structures have desirably been successfully scaled in dimension over the period of several decades to provide the particularly common, and highly useful, CMOS structure.
Among other avenues for CMOS device performance enhancement, recent advances in CMOS structure and CMOS device fabrication have included the use of separate gate materials for the fabrication of an nFET gate in comparison with a pFET gate in a CMOS structure. The use of such separate gate materials for fabrication of an nFET gate and a pFET gate in a CMOS structure allows for tuning of a particular work function of a particular nFET gate or pFET gate, which in turn allows for optimization of performance of an individual nFET device or pFET device in a particular CMOS structure. While the use of such separate gate materials for nFET gate and pFET gate fabrication within CMOS structures is thus desirable within the context of CMOS structure and CMOS device fabrication, the use of such separate gate materials for nFET gate and pFET gate fabrication in CMOS structures and CMOS devices is not entirely without problems. In that regard, the use of separate gate materials within nFET gates and pFET gates in CMOS structures and CMOS devices often provides manufacturing complexity.
Various CMOS structures and CMOS devices are known in the semiconductor fabrication art.
For example, Lee et al., in U.S. Pat. No. 6,653,698, teaches a dual work function CMOS structure. This particular dual work function CMOS structure includes a first gate that comprises a laminate of a first metal and a second metal upon the first metal, and a second gate that comprises a laminate of a third metal and the second metal upon the third metal.
In addition, Polishchuk, in U.S. Pat. No. 6,794,234, also teaches a dual work function CMOS structure. This particular dual work function CMOS structure comprises a first gate that comprises a first metal, and a second gate that comprises a second metal and an alloy of the first metal and a second metal located upon the second metal.
Finally, Park et al., in “Thermally Robust Dual-Work Function ALD-MNx MOSFET Using Conventional CMOS Process Flow,” VLSI 2004 teaches a dual work function CMOS structure that may be fabricated using conventional CMOS processing. This particular dual work function CMOS structure uses polysilicon/metal nitride gates.
Novel semiconductor structures and semiconductor devices, including in particular CMOS structures and CMOS devices, are certain to continue to be prevalent as semiconductor technology advances. Thus, desirable are semiconductor structures and semiconductor devices, such as CMOS structures and CMOS devices, with enhanced performance and enhanced manufacturability.